DMOS transistors, particularly of the vertical type, are of increasing importance as power transistors. A vertical DMOS transistor basically includes source and drain regions of one conductivity type on opposite surfaces of a semiconductive chip and a gate region of the opposite conductivity type on one surface between the source and drain regions. The gate region characteristically has been formed by diffusion of a first dopant into that portion of the chip to locally reverse there the original conductivity type. Typically this diffusion is first used to form a well within which there later is diffused a second dopant of the type opposite the first dopant to form an enclosed region or island of the original conductivity type that serves as the source region.
Appropriate voltages applied to an insulated doped-polysilicon gate electrode localized over a surface of this gate region induce a surface channel of the opposite conductivity type which effectively electrically connects together the source and drain regions. This facilitates a vertical current flow through the transistor between the drain and source regions on opposite surfaces of the chip. Typically the vertical DMOS structure utilizes an electrode to the source region that also electrically contacts or shorts to the diffused gate region.
In a typical conventional process for fabricating such a vertical DMOS device, at least two separate steps are used in doping appropriately the polysilicon gate electrode, the source region and the backside of the chip where the drain electrical contact is made. Additionally, usually the formation of the shorting source contact is a relatively complex operation involving many steps. These all add to the number of steps required in the manufacture of a DMOS type. Typically the cost increases and the yield decreases as the number of steps in the manufacture of a semiconductor device increases.
The present invention seeks to reduce the number of steps used in the manufacture of a semiconductor device.